Dynamic integrated circuit memory such as a random access memory (DRAM) traditionally stores data as a charge on memory cells. Each memory cell comprises a capacitor capable of holding a charge and a transistor for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Data can be stored in the memory cells during a write mode, and data may be retrieved from memory cells during a read mode. Data is transferred internally on signal lines which are commonly referred to as bit or digit lines. A typical DRAM is designed to have pairs of digit lines coupled to the memory cells, a single pair is commonly referred to as DIGIT and DIGIT*. The memory cell capacitors are charged or discharged through access transistors which are activated by other signal lines or word lines.
The capacitance of each memory cell in an integrated circuit is very small due to the small size of capacitors used to obtain a dense population of memory cells. Therefore, the available charge is proportionally small for each memory cell. For a reliable read of the memory cell capacitor charge, the charge must be sensed and amplified. A sense amplifier is essentially a differential amplifier designed to perform the sense and amplify operation.
The sense and amplify operation involves the detection and amplification of charge or the absence thereof in the memory cell capacitor. When a word line coupled to a cell access transistor transitions to a voltage that is at least one threshold voltage (Vt) above VEQ, which is also the initial value VEQ of both DIGIT and DIGIT*, the cell capacitor is discharged onto the digit line (cell-to-DIGIT) provided that the cell capacitor is initially charged. Otherwise if the cell capacitor had no charge initially then it will be charged (DIGIT-to-cell). In either case, cell-to-DIGIT discharge or DIGIT-to-cell charge, a differential voltage (dV) occurs between DIGIT and DIGIT*.
There are several different designs and implementations of sense amplifiers available. In one design disclosed in U.S. Pat. No. 5,042,011 to Casper, a sense amplifier comprises a pair of cross-coupled transistors and a single switched pulldown transistor device designed to turn the sense amplifier on by pulling down the common node of the sense amplifier's transistors to a reference potential voltage (VREF). In the case of cell-to-DIGIT discharge, DIGIT voltage VEQ is slightly increased to VEQ+dV while DIGIT* remains at VEQ resulting in DIGIT having a higher voltage than DIGIT*. When the pulldown device is activated, the sense amplifier gated by DIGIT will turn on faster than the sense amplifier gated by DIGIT*. Consequently, the transistor gated by DIGIT pulls DIGIT* from VEQ to VREF, while DIGIT remains at approximately VEQ+dV. Similarly, in the case of DIGIT-to-cell discharge, DIGIT is slightly decreased to VEQ-dV, while DIGIT* remains at VEQ. Therefore when the pulldown device is activated, DIGIT will be pulled down to VREF, while DIGIT* remains approximately at VEQ.
The pulldown device discussed above is driven by a pulldown driver consisting of a CMOS inverter. In use, when triggered by the output signal of the CMOS inverter, the pulldown device is turned on slowly, then quickly enters into saturation. Consequently, the sense amplifier common node is pulled down slowly, then quickly. The pulldown device needs to be pulled down quickly so the sense amplifier can perform the read of memory cell faster resulting in a faster speed of the DRAM. However, if the pulldown is too quick, the capacitive coupling between the sources and drains of the sense amplifier transistors tends to pull both DIGIT and DIGIT* down before the common node is pulled down low enough to turn on only one of the transistors. In this case when both of the transistors are turned on, it shorts out its capacitive coupling and bounces both DIGIT and DIGIT* and thus undesirable noise occurs. Therefore the slow-quick switching method is needed to pull down the common node of the sense amplifier. To achieve this slow-quick switching method, the pulldown device must receive a signal with a slow rising edge at the output of the pulldown driver. The CMOS inverter of the pulldown driver was designed to achieved this technique. To do so, the CMOS inverter must have a p-to-n transistor size ratio of about 0.8 to create a slow rising edge. Also, the input signal to the input of the CMOS inverter must be a slow high-to-low edge rate.
There is a need for an improved design for the pulldown driver.